1. Field of the Invention
This invention concerns a semiconductor device, and more particularly an improvement of the wiring pattern connection to a contact hole thereof.
2. Description of the Prior Art
Conventionally, to form an electrical path between a wiring layer and a source or a drain region in a MOS type semiconductor device, an underlying diffused region is formed to be connected with the wiring layer, which is formed at the formation of the gate electrode and made of the same material as the gate electrode.
FIGS. 1A and 1B show an example of such a prior art wiring arrangement. FIG. 1A is a plan view, and FIG. 1B is a cross sectional view along the line B-B' of FIG. 1A. In FIG. 1B, numeral 1 designates a semiconductor substrate, and numeral 2 designates an underlying diffused layer. Numeral 3 is a device separation region, and numeral 4 is a source or drain region (hereafter called as a source region). Numeral 8 is a gate insulating layer, and numeral 9 is a wiring layer of multi-layer construction composed of a poly-Si layer 6 and a refractory metal layer 7. As shown in FIG. 1A, the wiring layer 9 contacts with the underlying diffused layer 2 within the contact hole 10.
The fabrication process of the device is as follows. After the formation of the contact hole 10, a poly-Si layer doped with impurities is deposited, and a thermal treatment is carried out to form the underlying diffused layer 2 by diffusing impurities from the poly-Si layer to the substrate. Next, a refractory metal layer is deposited on the poly-Si layer to lower the resistance. Next, an etching process is carried out to pattern and make a patterned wiring layer 9. The condition of the etching is chosen so that the gate insulating layer 8 is not etched during this process.
However, in this construction, the leading edge of the wiring layer 9 ends within the contact hole 10. Thus, in the etching process, the exposed substrate between the insulating layer 8 and the wiring layer 9 is etched, and a trench region 5 is formed. Next, an ion implantation is carried out to form a source and a drain regions at the surface of the substrate, using the wiring layer 9 as a mask. Numeral 4A designates a diffused region formed at the implantation step.
The trench region 5 intersects the underlying diffused region 2. Thus, the conductive path between the wiring layer 9 and the source region 4 is cut off. Therefore. it is necessary to form the underlying diffused layer 2 deeply to avoid the discontinuity due to the trench region 5. However, deep diffusion of the underlying diffused region 2 is unfavorable for high integration of elements.
FIGS. 2A and 2B show another example of conventional wiring pattern. FIG. 2A is a plan view, and FIG. 2B is a cross sectional view along the line B-B' of FIG. 2A. In this example. the wiring layer 29 covers the contact hole 30 completely. The formation step is the same to that of FIGS. 1A and 1A.
In this example, the substrate within the contact hole 30 is not exposed to the etching process for the patterning of the wiring layer 29. Thus, there is no formation of the unfavorable trench region like FIG. 2B. However, there may exist an un-implanted region 20 between the underlying diffused region 22 and the source (or drain) region 24. Thus, in this construction, it is necessary to deeply form the underlying diffused region 22, so as to connect the regions 22 and 24, using a lateral diffusion of the underlying diffused region 22. The deep formation of the region 22 is unfavorable for high integration of elements.